IMPACT OF GEOMETRICAL SCALING ON PARASITIC PNP BIPOLAR-TRANSISTOR IN N-WELL, 0.25 MU-M CMOS DEVICES AND ITS EFFECT ON LATCHUP IMMUNITY

This paper presents a detailed analysis of latchup dependence on geome trical dimensions of N-well, 0.25 mu m complementary metal-oxide silic on (CMOS) devices with 50 Angstrom gate oxide using simulation and exp eriment. Simulation results show that as dimensions continue to shrink , the traditionally accepted vertical parasitic pnp bipolar transistor becomes a lateral device. This observed result is very significant si nce increasing the N-well junction depth no longer guarantees improvem ent in latchup immunity. Experimental data shows that variation in pf emitter to N-well edge spacing (d(plat)) does not affect latchup chara cteristics as long as d(plat) is far greater than d(pver), the differe nce between the N-well and p+ diffusion junction depth. (C) 1998 Elsev ier Science Ltd. All rights reserved.