READ-DISTURB AND ENDURANCE OF SSI-FLASH E(2)PROM DEVICES AT HIGH OPERATING TEMPERATURES

The high-temperature (T) reliability behavior of merged-transistor sou rce side injection (SSI) Flash nonvolatile memory (NVM) devices is eva luated in terms of endurance and disturb effects related to stress ind uced leakage current (SILC), and correlated with the high-T behavior ( generation, anneal) of oxide traps. As compared to room-T, program/era se (P/E) cycling at 150 degrees C results in an improved endurance due to an enhanced charge emission. The impact of the operating temperatu re on SILC-related disturb effects, on the other hand, depends on two combined effects in memory cells where large local charge trap-up infl uences the threshold voltage, V-t: 1) the T-enhanced trap generation a nd 2) the T-enhanced emission of trapped charge which influences the d isturb field. In the case of the HIMOS-cell-which is discussed here-lo ng-term nonvolatility can still be guaranteed at 150 degrees C. Finall y, bake tests at higher temperatures (250-300 degrees C) have been per formed in order to evaluate the persistence of the generated damage, I t is found that bulk oxide traps are not cured by the bake and, theref ore, no long-term relief of SILC-related disturb effects is expected a t 150 degrees C.