PIPELINED H-TREES FOR HIGH-SPEED CLOCKING OF LARGE INTEGRATED SYSTEMSIN PRESENCE OF PROCESS VARIATIONS

This paper addresses the problem of clocking large high-speed digital systems, as well as deterministic skew modeling, a related problem. A conventional method for clocking a large digital system is to use a se t of metallic lines organized as a tree. This method is limited by the bandwidth of the clock network, Another limitation of existing soluti ons is that available skew models do not directly take into account pr ocess variations, In order to provide a reliable skew model, and to av oid the frequency limitation, we propose a novel approach that distrib utes the clock with an H-tree, whose branches are composed of minimum- sized inverters rather than metal. With such a structure, we obtain th e highest clocking rate achievable with a given technology, Indeed, cl ock rates around 1 GHz are possible with a 1.2 mu m CMOS technology. F rom the skew modeling standpoint, we derive an analytic expression of the skew between two leaves of the H-tree, which we consider to be the difference in root-to-leaf delay pairs, The skew upper bound obtained has an order of complexity which, with respect to the H-tree size D, is the same as the one that may be derived from the Fisher and Kung mo del for both side-to-side and neighbor-to-neighbor communications, i.e ., a Omega(D-2), whereas, the Steiglitz and Kugelmass probabilistic mo del predicts Theta(D x root LogD). In an H-tree implemented with metal lic lines, the leaf-to-leaf skew is obviously bounded by the delay bet ween the root and the leaves, However, with the logic based H-tree pro posed in this paper, we arrive at a nonobvious result, which states th at the leaf-to-leaf skew grows faster than the root-to-leaf delay in p resence of a uniform transistor time constant gradient, This paper als o proposes generalizations of the skew model to 1) the case of chips i n a wafer subject to a smooth, but nonuniform gradient and 2) the case of H-tree configurations mixing logic and interconnections; in this r espect, this paper covers the H-tree configurations based on the combi nation of logic and interconnections.