DIAGNOSIS AND CORRECTION OF MULTIPLE LOGIC DESIGN ERRORS IN DIGITAL CIRCUITS

This paper presents a technique to correct multiple logic design error s in a gate-level netlist. A number of methods have been proposed for correcting single logic design errors [1]-[10]. However, the extension of these methods to more than one error is still very limited. We dir ect our attention to circuits with a low multiplicity of errors. By as suming different error dependency scenarios, multiple errors are corre cted by repeatedly applying the single error search and correction alg orithm proposed in [7]. Experimental results on correcting double-desi gn errors and triple-design errors on ISCAS and MCNC benchmark circuit s are included.