DESIGN OF A 32 B MONOLITHIC MICROPROCESSOR-BASED ON GAAS HMESFET TECHNOLOGY

This paper examines the design of a 32-b GaAs Fast RISC microprocessor (F-RISC/I). F-RISC/I is a single chip GaAs HMESFET professor targeted for implementation on a multichip module (MCM) together with cache me mories, The CPU architecture, circuit design, implementation, and test ing are optimized for a seven-stage instruction pipeline implemented w ith GaAs super-buffered PET logic (SBFL). We have been able to verify novel GaAs SBFL standard cells and compare measured CPU performance wi th performance estimates based on circuit and device models. The proto type 32-b microprocessor has been implemented using an automated stand ard cell approach because of time constraints and fabricated using an experimental process by Rockwell International. The CPU chip integrate s 92340 transistors on a 7 x 7 mm(2) die and dissipates 6.13 W at 180 MHz. Test results from a prototype fabrication run have demonstrated t he operation of the ALU, the program counter, and the register file wi th delays below 6, 5, and 3.4 ns, respectively, The successful modelin g and verification indicate that a 0.5 mu m HMESFET implementation of F-RISC/I could achieve a peak performance of 350 MHz. The miring delay s account for 42% of the critical path delay.