OPTIMAL FAULT-TOLERANT DESIGN APPROACH FOR VLSI ARRAY PROCESSORS

Authors
ZHANG CN BACHTIAR TM CHOU WK
Citation
Cn. Zhang et al., OPTIMAL FAULT-TOLERANT DESIGN APPROACH FOR VLSI ARRAY PROCESSORS, IEE proceedings. Computers and digital techniques, 144(1), 1997, pp. 15-21
Citations number
15
Categorie Soggetti
Computer Sciences","Computer Science Hardware & Architecture","Computer Science Theory & Methods
Journal title
IEE proceedings. Computers and digital techniques → ACNP
ISSN journal
13502387
Volume
144
Issue
1
Year of publication
1997
Pages
15 - 21
Database
ISI
SICI code
1350-2387(1997)144:1<15:OFDAFV>2.0.ZU;2-V
Abstract
A systematic approach for designing a fault-tolerant systolic array us ing space and/or time redundancy is proposed. The approach is based on a fault-tolerant mapping theory which relates space-time mapping and concurrent error detection techniques. By this design approach, the re sulting systolic array is fault tolerant and achieves the optimal spac e-time product. In addition, it has the capability to compute more pro blem instances simultaneously without extra cost.