DESIGN AND IMPLEMENTATION OF HOPFIELD NEURAL-NETWORK USING VHDL STRUCTURAL MODELING

The authors present a technique for hardware realization of a discrete Hopfield artificial neural network. The technique is fast and expanda ble, and produces a VHDL code describing the specifics of the network' s architecture. The user specifies the size of the network and the tra ining data st the time of compilation. The design of the network is pu rely structural VHDL that allows tight control over all primitives. A synthesis program (Viewsynthesis) is used on the structural design to realize a six-neuron Hopfield network on a Xc4000 Field Programmable A rrays (FPGAs) chip. The network is trained to recognize simple seven-s egment patterns. The authors have successfully tested the network.