GATE TECHNOLOGY FOR 0.1-MU-M SI COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR USING G-LINE EXPOSURE AND DEEP-ULTRAVIOLET HARDENING

A gate technology for producing 0.1-mum gate length silicon complement ary metal-oxide-semiconductor (CMOS) circuits has been developed by in tegrating g-line exposure, resist narrowing, deep UV hardening, and dr y etching of nitride and polysilicon. The 0.1-mum gate length n-channe l and p-channel MOS devices have been previously processed via e-beam lithography using a chemically amplified e-beam resist. However, the e -beam technique suffers from low throughput, especially in processing complex circuits. In addition, the chemically amplified e-beam resist requires prompt processing. Thus g-line exposure and photoresist narro wing was chosen as an alternative. The resist features were narrowed f rom 0.5 mum down to 0.1 mum using low power O2 plasma. The profile of the narrowed resist shows that the body is thicker than the base. The narrowed resist features were then hardened by deep UV in order for th e photoresist to withstand the subsequent nitride etch using CHF3 reac tive ion etching (RIE). The obtained nitride profile shows a rounded t op which is expected from the profile of resist features. The subseque nt polysilicon etch was done using a two-step Cl2 RIE. The obtained pr ofile of polysilicon is comparable to that previously obtained using e -beam lithography. This gate technology was used to successfully fabri cate 0.1-mum circuits such as conventional unloaded CMOS ring oscillat ors and 2:1 frequency dividers.