STOCHASTIC-MODEL OF A CACHE-COHERENCY OVERHEAD IN SCI RINGS

The authors present a new analytical performance model of the IEEE P15 96 Standard Coherent Interface, which is a distributed cache-coherency protocol for shared-memory multiprocessors. The paper focuses upon an implementation of the protocol on a unidirectional ring architecture (the 'default' architecture for SCI systems). The authors identify the possible memory and cache-line states and corresponding processor act ions for a memory access, and derive the equilibrium line state probab ilities by solving a Markov model expressed as a set of fixed-point eq uations. The probabilities of a processor performing a particular acti on then follow, from which the message transmission profile for each p rocessor is derived. These traffic equations are then fed into an M/G/ 1 model for the ring architecture, in which the ring traffic at a node has priority over traffic originating in that node. Further analysis then leads to the mean message transmission time, and hence the mean m emory access time and processor utilisation. The application of the mo del is illustrated by undertaking a performance comparison of two alte rnative node architectures and some numerical results are reported for various parameterisations.