M. Depas et Mm. Heyns, RELATION BETWEEN TRAP CREATION AND BREAKDOWN DURING TUNNELING CURRENTSTRESSING OF SUB 3 NM GATE OXIDE, Microelectronic engineering, 36(1-4), 1997, pp. 21-24
The wear-out of sub 3 nm gate oxide layers during tunnelling current s
tressing has been characterised by charge to breakdown (Q(BD)), tunnel
current instability and stress induced leakage current (SILC) measure
ments. A correlation is found between the maximum value of the Q(BD) d
istribution and the amount of SILC for different tunnelling current st
ress conditions. The experimental results are consistent with the oxid
e breakdown model based on electron trap creation.