CAPACITANCE MEASUREMENTS ON SIC MOS STRUCTURES FOR THE DETERMINATION OF INTERFACE PROPERTIES

C-V characteristics of metal-insulator-semiconductor (MIS) structures based on GH-SiC are investigated. These characteristics are influenced by non-equilibrium charge carrier conditions at the insulator-semicon ductor interface. Depending on the sweep rate of the bias voltage the traps exhibit either thermal- or non-thermal equilibrium behaviour. Ti mes needed to approach thermal equilibrium may be of the same order or much longer than times spent on the measurement procedure. In the pre sent paper we give a simple model of the interface charge carrier dyna mics for the interpretation of measurement data from GH-SiC MOS struct ures and demonstrate how high frequency C-V data can be used to assess the oxide-SiC interface. However a quantitative analysis of data is y et difficult because of the influence of the measurements themselves o n the C-V response of our devices.