EFFECTS OF HOT-CARRIER DEGRADATION IN ANALOG CMOS CIRCUITS

In this paper a method is presented that allows to quantify the effect s of hot carrier degradation on analog CMOS circuits. Specific feature s of hot carrier degradation related to analog CMOS operation are disc ussed in detail. On this basis single transistor stress experiments ar e defined monitoring analog operation and conclusions are drawn for th e choice of analog hot carrier lifetime criteria. A general method is presented which establishes a relation between single transistor stres s results and circuit parameter degradation. Examples for the applicab ility of this method are given, presenting measured data of hot-carrie r-induced parameter shifts of analog sub-circuits.