The article describes, in terms of steady-state sinusoidal analysis, s
imple analytical expressions for the operating speed and power consump
tion of DCFL D-type Aip-flops. The maximum operating speed f(OPmax) is
limited to f(T) sin{pi/(n(G) + 1)}/2n(FO), where f(T) is the cut-off
frequency, n(G) is the number of critical path gates, and n(FO) is the
fan-out number. In contrast, the influence of maximum frequency of os
cillation f(max) on f(OPmax) is small compared with that for f(T), but
an FET with a higher f(max) can reduce the power consumption. These a
nalytical results agree well with the experimental results. (C) 1997 P
ublished by Elsevier Science Ltd.