Decreasing the field oxide thickness, increasing the temperature or ox
idation pressure in a LOGOS type isolation improves field oxide thinni
ng. Under the above regimes, the bird's beak growth results from a rea
ction-limited mechanism during the linear part of the oxidation proces
s. The latter property is of major importance for the future shrink of
LOGOS isolation towards sub-0.1 mu m CMOS designs. Market pressure, b
ecause of the strong demand fbr low-voltage and low-power ULSI devices
, is defining the framework. Matching the trend in depth-of-focus redu
ction in lithography tools and limiting process complexity will have t
o be weighed constantly. The reduction oi isolation dimension losses t
o zero is not as urgent as it used to be. Shallow trench isolation has
not come to maturity because of the technically difficult and economi
cally practicable trade-off to be found between planarization and devi
ce leakage. Refilling and planarization process standards have not yet
been established despite the major progress made in chemical mechanic
al polishing. The contradiction betwen the planarization issue and the
need for an abrupt step at the isolation/active-area edge in order to
avoid subthreshold leakage of the MOS active sidewalls still has to b
e solved. After a brief historical review, we point out and reconsider
the main advantages and drawbacks of LOGOS type and shallow trench is
olation processes. Within that framework, the impact of isolation desi
gn rules on device integration density and isolation performance is re
viewed and commented on. (C) 1997 Elsevier Science Ltd.