Design and development challenges for micro chip carrier

Citation
Yj. Park et al., Design and development challenges for micro chip carrier, PROCEEDINGS OF 3RD ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, 2000, pp. 308-314
Citations number
7
Categorie Soggetti
Current Book Contents
Year of publication
2000
Pages
308 - 314
Database
ISI
SICI code
Abstract
The development of size and cost-effective leadframe based package to repla ce the conventional packages such as TSSOP, TQFP with the same or the bette r package integrity and electrical performance is getting critical to penet rate into the future wireless subscriber applications. In this report, the development of 0.9mm thick MO-208 Thin Fine Pitch Plastic Quad Flat No Lead Package (5x5mm, 28 leads, 0.5mm pitch) with Moisture Sensitivity Level (MS L) 1 reliability is discussed. Technical challenges for the development of package MO-208, called Micro Chip Carrier in ASE Korea, are to control the mechanical impact to lead after Mold Array Package (MAP) and to reduce the die stress with leadframe design based on the various simulation processes. No mechanical impact to lead after mold has been found to be a critical fa ctor to control the package integrity and to increase the lifetime of saw b lade. it was also discovered that the package under development is able to achieve JEDEC MSL 1 reliability criteria. This paper discusses the package and process development performed in order to meet these new wireless subsc riber application requirements. Our benchmark and internal evaluation suppo rted our approaches and our Micro Chip Carrier(MCC) technology is very comp etitive to leading the market share.