Design of encapsulating materials for advanced area bump packages

Now, over 5 billion units of ICs are produced in every month in the entire world. Almost all of them are protected from the affect of environmental st ress such as, humidity, heat, mechanical stress, and pollutions, when insta lled in actual electronics devices. On the other hand, higher frequency and higher I/O trends require shorter e lectrical pass length in the packages. Flip Chip package is one of the best solutions for the above requirements. This package has been expanding in f ront edge micro processors and the peripheral ICs. The next market requirem ent for flip chip package is low cost and mass production flip chip packagi ng for conventional ICs, For the purpose of cost reduction with mass produc tion, transfer molding for flip chip packaging has been studied. The even n ow to thin and thick gap is required for this package and process. By contr olling filler particle size, flow balance was well controlled. As the resul t, good potential of transfer under-fill was observed in this study. The plastic substrate is another solution for cost reduction and higher fre quency applications. However there is one major concerning point to use pla stic substrate. It is thermal expansion (CTE) miss match between substrate and silicon chip. It causes poor thermal shock reliability. The preset unde r-fill with clamping cure process gave good sign to improve thermal shock p erformance for plastic substrate flip chip package.