Applications of newly developed positive photosensitive block co-polyimides to CSPs

Meeting the challenging market-defined needs of CSPs (chip sized packages) industry requires a new substrate technology that provides higher I/O densi ties, higher performance, thinner and lighter packaging structures than pre viously available solutions. In this paper, the first applications to CSP i nterposer (CSP-IP) processes by newly developed positive photosensitive blo ck co-polyimides (PPI), which P I R&D Co., Ltd. of Japan has commercialized recently, are discussed. Block co-polyimides are prepared in organic polar solvents by the sequentia l addition co-polymerization process in the presence of the binary catalyst , which has been described in US patents by the author. PPI polymer solutio ns are derived from block co-polyimides including photo-sensitizers. Advant ages of newly developed PPIs from block co-polyimides are as follows; 1) no imidization process needs at high temperature, 2) PPIs have strong adhesiv e ability to Cu, Al and Si wafers, 3) thinner thickness polyimide films are available with high durability, 4) positive photo-pattern are available wi th high resolution, 5) PPIs are high temperature Tg materials. In CSP-IP packaging processes by PPI, it is shown that PPI's UV-lights reso lution workability brings highly uniformed 20 microns diameter via hole, an d also, highly uniformed solder bumps attached on the polyimides layers. PPI requires no imidization process after drying and curing in the processe s, accordingly, the whole heat requirements in the CSP-IP processes are bel ow 200 degreesC, which enables to CSP-IP the additional layers of lead I/O patterning between solder bumps interstice without any solder bump deformat ions, that provides higher I/O densities, size reductions to the new CSP-IP . PPI's pin-holeless performance using black masks processes brings CSP-IP production cost keeps very low-level, and it is possible to coat PPI polyme r solution directly on silicon wafer easily and to produce the wafer CSP wi th high production yield, which keep this wafer CSP processes quite a compe titive low cost. Thinner layered CSP-IP packages by PPI described above cou ld be applied to the 3D-stacked CSP package features.