Analysis of the output characteristics of the Dual Channel EST (DC-EST
) is. provided for the first time in this article. It is demonstrated
by analytical modelling and with the aid of two dimensional numerical
simulations that the output resistance in the region of current satura
tion is determined by the activation of the narrow base NPN transistor
in the IGBT segment. Based upon this model, the experimentally observ
ed degradation in the output resistance with an increase in the distan
ce between the shorts in the P-base region of the main thyristor segme
nt can be explained. This model is shown to be consistent with the exp
erimentally observed degradation in the output resistance with larger
design rules used for device fabrication because this determines the c
urrent level at which the NPN transistor becomes activated. The observ
ed reduction in the output resistance results in a degradation in the
forward bias safe operating area. (C) 1997 Elsevier Science Ltd.