I-DDQ DETECTABLE BRIDGES IN COMBINATIONAL CMOS CIRCUITS

Undetectable stuck-at faults in combinational circuits are related to the existence of logic redundancy (s-redundancy). Similarly, logically equivalent nodes may cause some bridging faults to become undetectabl e by I-DDQ testing. An efficient method for the identification and rem oval of such functionally equivalent nodes Oc-redundant nodes) in comb inational circuits is presented. OBDD graphs are used to identify the functional equivalence of candidate to f-redundancy nodes. An f-redund ancy removal algorithm based on circuit transformations to improve bri dging fault testability, is also proposed. The efficiency of the ident ification and removal of f-redundancy has been evaluated on a set of b enchmark circuits.