VLSI TESTING FOR HIGH-RELIABILITY - MIXING I-DDQ TESTING WITH LOGIC TESTING

In this paper, we examine the effectiveness of combined logic and I-DD Q testing to detect stuck-at and bridging faults. The stuck-at faults are detected by the logic test and I-DDQ testing detects bridging faul ts. Near minimal stuck-at test sets are used for this combined logic a nd I(DDQ)nvironment. These near minimal stuck-at test sets are generat ed using standard test programs, while using collapsed fault lists. We examined ISCAS '85 and ISCAS '89 benchmark circuits under this combin ed test environment. A comparison is given for the fault coverage obta ined under this combined test environment with other studies based on pure logic test and I-DDQ test. Also, the results of I-DDQ based test sets (vectors generated specifically for I-DDQ testing) are compared w ith that of stuck-at test sets. Finally, we present a case study on a microprogrammed processor using a functional test set to detect bridgi ng faults in I-DDQ testing.