GRAIN-BOUNDARY POTENTIAL BARRIER INHOMOGENEITIES IN LOW-PRESSURE CHEMICAL-VAPOR-DEPOSITED POLYCRYSTALLINE SILICON THIN-FILM TRANSISTORS

Arrhenius plots of conductivity in low-pressure chemical vapor deposit ed (LPCVD) polycrystalline silicon thin-film transistors (TFT's) are c urved when the films are deposited at pressures below 40 mtorr. These deviations from straight lines are explained by spatial potential fluc tuations over the grain boundary plane described by a Gaussian type di stribution. When grain boundary inhomogeneities are not taken into acc ount, the determined trap states density and the threshold voltage of the transistor are underestimated.