A RECONFIGURABLE VLSI COPROCESSING SYSTEM FOR THE BLOCK MATCHING ALGORITHM

Several VLSI architectures for the full-search block matching algorith m have been proposed in recent years due to its computation and I/O-in tensive nature and its importance in various computer vision and image processing applications, This paper presents a new coarse grained rec onfigurable coprocessor which is suitable for integration with general purpose microprocessors. The 180 000 transistor custom VLSI design wa s implemented in 0.6 mu m CMOS on a 4.12 mm x 2.59 mm die and has been fully tested up to 33 MHz. For a typical image database search applic ation, a sample system consisting of four coprocessors interfaced thro ugh a 33 MHz PCI bus will provide a speedup of 320x over an 80486 DX2/ 66 MHz and 64x over a 150-MHz Pentium running fully optimized assembly code.