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Results:
1-7
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Results: 7
Authors:
ACOSTA AJ
JIMENEZ R
BARRIGA A
BELLIDO MJ
VALENCIA M
HUERTAS JL
Citation: Aj. Acosta et al., DESIGN AND CHARACTERIZATION OF A CMOS VLSI SELF-TIMED MULTIPLIER ARCHITECTURE BASED ON A BIT-LEVEL PIPELINED-ARRAY STRUCTURE, IEE proceedings. Circuits, devices and systems, 145(4), 1998, pp. 247-253
Authors:
JUANCHICO J
BELLIDO MJ
ACOSTA AJ
VALENCIA M
HUERTAS JL
Citation: J. Juanchico et al., ANALYSIS OF METASTABLE OPERATION IN A CMOS DYNAMIC D-LATCH, Analog integrated circuits and signal processing, 14(1-2), 1997, pp. 143-157
Authors:
JUANCHICO J
BELLIDO MJ
ACOSTA A
BARRIGA A
VALENCIA M
Citation: J. Juanchico et al., CMOS INVERTER MAXIMUM FREQUENCY OF OPERATION DUE TO DIGITAL SIGNAL DEGRADATION, Electronics Letters, 33(19), 1997, pp. 1619-1621
Authors:
BELLIDO MJ
ACOSTA AJ
LUQUE J
BARRIGA A
VALENCIA M
Citation: Mj. Bellido et al., EVALUATION OF METASTABILITY TRANSFER MODELS - AN APPLICATION TO AN N-BISTABLE CMOS SYNCHRONIZER, International journal of electronics, 79(5), 1995, pp. 585-593
Authors:
VALENCIA M
BELLIDO MJ
HUERTAS JL
ACOSTA AJ
SANCHEZSOLANO S
Citation: M. Valencia et al., MODULAR ASYNCHRONOUS ARBITER INSENSITIVE TO METASTABILITY, I.E.E.E. transactions on computers, 44(12), 1995, pp. 1456-1461
Authors:
ACOSTA AJ
VALENCIA M
BARRIGA A
BELLIDO MJ
HUERTAS JL
Citation: Aj. Acosta et al., SODS - A NEW CMOS DIFFERENTIAL-TYPE STRUCTURE, IEEE journal of solid-state circuits, 30(7), 1995, pp. 835-838
Authors:
ACOSTA AJ
VALENCIA M
BARRIGA A
BELLIDO MJ
HUERTAS JL
Citation: Aj. Acosta et al., DESIGN, TESTING AND APPLICATIONS OF 4-VALUED PADS, International journal of electronics, 75(1), 1993, pp. 115-131
Risultati:
1-7
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