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Results: 4
ASYNCHRONOUS DESIGN - NIGHTMARE OR OPPORTUNITY
Authors:
BRULS E
Citation:
E. Bruls, ASYNCHRONOUS DESIGN - NIGHTMARE OR OPPORTUNITY, IEEE design & test of computers, 14(1), 1997, pp. 84-85
ANALOG FAULT SIMULATION IN STANDARD VHDL
Authors:
BRULS E VERSTRAELEN M ZWEMSTRA T MEIJER P
Citation:
E. Bruls et al., ANALOG FAULT SIMULATION IN STANDARD VHDL, IEE proceedings. Circuits, devices and systems, 143(6), 1996, pp. 380-385
QUALITY AND RELIABILITY IMPACT OF DEFECT DATA-ANALYSIS
Authors:
BRULS E
Citation:
E. Bruls, QUALITY AND RELIABILITY IMPACT OF DEFECT DATA-ANALYSIS, IEEE transactions on semiconductor manufacturing, 8(2), 1995, pp. 121-129
TOTALLY SELF-CHECKING CMOS CIRCUIT-DESIGN FOR BREAKS AND STUCK-ON FAULTS - COMMENTS
Authors:
BRULS E SACHDEV M BAKER K
Citation:
E. Bruls et al., TOTALLY SELF-CHECKING CMOS CIRCUIT-DESIGN FOR BREAKS AND STUCK-ON FAULTS - COMMENTS, IEEE journal of solid-state circuits, 28(10), 1993, pp. 1056-1057
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