In the last decade we have seen a shift towards a broader application
of information on IC manufacturing defects. Here an overview will be g
iven of the methods used to gather data on the defects with a focus on
local defects in the interconnection layers. Next this information is
applied to determine a model describing the geometrical aspects of su
ch defects. This model is used to come to the definition of hard fault
s and soft faults and to derive a relationship between the relative nu
mber of occurrence for either fault. Because the electrical impact of
some of the soft faults will be closely related to the behavior of sma
ll open circuits or gate-oxide shorts, this relationship is an indicat
ion for the amount of quality and reliability problems.