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Table of contents of journal: *IEEE Transactions on semiconductor manufacturing

Results: 1-25/365
SPECIAL SECTION ON 1997 INTERNATIONAL WORKSHOP ON STATISTICAL METROLOGY
Authors: HOSACK HH MASUDA H
Citation: Hh. Hosack et H. Masuda, SPECIAL SECTION ON 1997 INTERNATIONAL WORKSHOP ON STATISTICAL METROLOGY, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 525-526
AUTOMATIC SYNTHESIS OF EQUIPMENT RECIPES FROM SPECIFIED WAFER-STATE TRANSITIONS
Authors: DAVIS JC MOZUMDER PK BURCH R FERNANDO C APTE PP SAXENA S RAO S VASANTH K
Citation: Jc. Davis et al., AUTOMATIC SYNTHESIS OF EQUIPMENT RECIPES FROM SPECIFIED WAFER-STATE TRANSITIONS, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 527-536
EFFICIENT MACROMODELING OF DEFECT PROPAGATION GROWTH MECHANISMS IN VLSI FABRICATION/
Authors: LI XL STROJWAS AJ REDDY M MILOR LS
Citation: Xl. Li et al., EFFICIENT MACROMODELING OF DEFECT PROPAGATION GROWTH MECHANISMS IN VLSI FABRICATION/, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 537-545
EFFECTS OF DEFECT PROPAGATION GROWTH ON IN-LINE DEFECT-BASED YIELD PREDICTION/
Authors: SHINDO W NURANI RK STROJWAS AJ
Citation: W. Shindo et al., EFFECTS OF DEFECT PROPAGATION GROWTH ON IN-LINE DEFECT-BASED YIELD PREDICTION/, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 546-551
SIMULATING THE IMPACT OF PATTERN-DEPENDENT POLY-CD VARIATION ON CIRCUIT PERFORMANCE
Authors: STINE BE BONING DS CHUNG JE CIPLICKAS DJ KIBARIAN JK
Citation: Be. Stine et al., SIMULATING THE IMPACT OF PATTERN-DEPENDENT POLY-CD VARIATION ON CIRCUIT PERFORMANCE, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 552-556
CIRCUIT SENSITIVITY TO INTERCONNECT VARIATION
Authors: LIN ZH SPANOS CJ MILOR LS LIN YT
Citation: Zh. Lin et al., CIRCUIT SENSITIVITY TO INTERCONNECT VARIATION, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 557-568
EXPRESSION OF WORST-CASE USING MULTIVARIATE-ANALYSIS IN MOSFET MODEL PARAMETERS
Authors: YASUDA T KAWASHIMA H HORI S TANIZAWA M YAMAWAKI M ASAI S
Citation: T. Yasuda et al., EXPRESSION OF WORST-CASE USING MULTIVARIATE-ANALYSIS IN MOSFET MODEL PARAMETERS, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 569-574
ACCURATE STATISTICAL PROCESS VARIATION ANALYSIS FOR 0.25-MU-M CMOS WITH ADVANCED TCAD METHODOLOGY
Authors: SATO H KUNITOMO H TSUNENO K MORI K MASUDA H
Citation: H. Sato et al., ACCURATE STATISTICAL PROCESS VARIATION ANALYSIS FOR 0.25-MU-M CMOS WITH ADVANCED TCAD METHODOLOGY, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 575-582
PLANNING WAFER ALLOCATION FOR CMOS PROCESS-DEVELOPMENT - A NONPARAMETRIC APPROACH
Authors: RAO S VASANTH K MOZUMDER PK SAXENA S DAVIS JC BURCH R
Citation: S. Rao et al., PLANNING WAFER ALLOCATION FOR CMOS PROCESS-DEVELOPMENT - A NONPARAMETRIC APPROACH, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 583-590
IMPROVEMENT IN THRESHOLD VOLTAGE CONTROL BY MINIMIZING BORON PENETRATION IN A LV-GCMOS TECHNOLOGY
Authors: JOHN JP TEPLIK JA HILDRETH SA XU S PARK C
Citation: Jp. John et al., IMPROVEMENT IN THRESHOLD VOLTAGE CONTROL BY MINIMIZING BORON PENETRATION IN A LV-GCMOS TECHNOLOGY, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 591-597
TEMPERATURE-MEASUREMENT OF WAFERS WITH VARYING MULTILAYER STRUCTURES DURING RAPID THERMAL ANNEALING
Authors: LERCH W BLERSCH W YANAGAWA S
Citation: W. Lerch et al., TEMPERATURE-MEASUREMENT OF WAFERS WITH VARYING MULTILAYER STRUCTURES DURING RAPID THERMAL ANNEALING, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 598-606
THE EFFECT OF SURFACE-ROUGHNESS ON THE RADIATIVE PROPERTIES OF PATTERNED SILICON-WAFERS
Authors: HEBB JP JENSEN KF THOMAS J
Citation: Jp. Hebb et al., THE EFFECT OF SURFACE-ROUGHNESS ON THE RADIATIVE PROPERTIES OF PATTERNED SILICON-WAFERS, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 607-614
AN EXTRACTION METHOD TO DETERMINE INTERCONNECT PARASITIC PARAMETERS
Authors: CHAO CJ WONG SC CHEN MJ LIEW BK
Citation: Cj. Chao et al., AN EXTRACTION METHOD TO DETERMINE INTERCONNECT PARASITIC PARAMETERS, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 615-623
A NEW 4-LEVEL METAL INTERCONNECT SYSTEM TAILORED TO AN ADVANCED 0.5-MU-M BICMOS TECHNOLOGY
Authors: WALL RN OLEWINE MC AUGUR R DIGREGORIO J COLOVOS G
Citation: Rn. Wall et al., A NEW 4-LEVEL METAL INTERCONNECT SYSTEM TAILORED TO AN ADVANCED 0.5-MU-M BICMOS TECHNOLOGY, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 624-635
MEASUREMENT AND CHARACTERIZATION OF MULTILAYERED INTERCONNECT CAPACITANCE FOR DEEP-SUBMICRON VLSI TECHNOLOGY
Authors: WEE JK PARK YJ MIN HS CHO DH SEUNG MH PARK HS
Citation: Jk. Wee et al., MEASUREMENT AND CHARACTERIZATION OF MULTILAYERED INTERCONNECT CAPACITANCE FOR DEEP-SUBMICRON VLSI TECHNOLOGY, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 636-644
A CVD EPITAXIAL DEPOSITION IN A VERTICAL BARREL REACTOR - PROCESS MODELING USING CLUSTER-BASED FUZZY-LOGIC MODELS
Authors: CHIOU JC YANG JY
Citation: Jc. Chiou et Jy. Yang, A CVD EPITAXIAL DEPOSITION IN A VERTICAL BARREL REACTOR - PROCESS MODELING USING CLUSTER-BASED FUZZY-LOGIC MODELS, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 645-653
A PROBABILISTIC APPROACH TO RUN-TO-RUN CONTROL
Authors: HAMBY ES KABAMBA PT KHARGONEKAR PP
Citation: Es. Hamby et al., A PROBABILISTIC APPROACH TO RUN-TO-RUN CONTROL, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 654-669
A STUDY ON FAILURE PREDICTION IN A PLASMA REACTOR
Authors: RIETMAN EA BEACHY M
Citation: Ea. Rietman et M. Beachy, A STUDY ON FAILURE PREDICTION IN A PLASMA REACTOR, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 670-680
MAXIMUM-LIKELIHOOD-ESTIMATION FOR FAILURE ANALYSIS
Authors: YU JL FERGUSON FJ
Citation: Jl. Yu et Fj. Ferguson, MAXIMUM-LIKELIHOOD-ESTIMATION FOR FAILURE ANALYSIS, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 681-691
MODELING MAGNETICALLY ENHANCED RIE OF ALUMINUM-ALLOY FILMS USING NEURAL NETWORKS
Authors: KIM B KWON K
Citation: B. Kim et K. Kwon, MODELING MAGNETICALLY ENHANCED RIE OF ALUMINUM-ALLOY FILMS USING NEURAL NETWORKS, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 692-695
INTRODUCTION TO THE SPECIAL SECTION ON PETRI NETS IN SEMICONDUCTOR MANUFACTURING
Authors: JENG MD ZHOU M
Citation: Md. Jeng et M. Zhou, INTRODUCTION TO THE SPECIAL SECTION ON PETRI NETS IN SEMICONDUCTOR MANUFACTURING, IEEE transactions on semiconductor manufacturing, 11(3), 1998, pp. 330-332
MODELING, ANALYSIS, SIMULATION, SCHEDULING, AND CONTROL OF SEMICONDUCTOR MANUFACTURING SYSTEMS - A PETRI-NET APPROACH
Authors: ZHOU MC JENG MD
Citation: Mc. Zhou et Md. Jeng, MODELING, ANALYSIS, SIMULATION, SCHEDULING, AND CONTROL OF SEMICONDUCTOR MANUFACTURING SYSTEMS - A PETRI-NET APPROACH, IEEE transactions on semiconductor manufacturing, 11(3), 1998, pp. 333-357
MODELING, QUALITATIVE-ANALYSIS, AND PERFORMANCE EVALUATION OF THE ETCHING AREA IN AN IC WAFER FABRICATION SYSTEM USING PETRI NETS
Authors: JENG MD XIE XL CHOU SW
Citation: Md. Jeng et al., MODELING, QUALITATIVE-ANALYSIS, AND PERFORMANCE EVALUATION OF THE ETCHING AREA IN AN IC WAFER FABRICATION SYSTEM USING PETRI NETS, IEEE transactions on semiconductor manufacturing, 11(3), 1998, pp. 358-373
MODELING AND SIMULATION OF AN ELECTRONIC-COMPONENT MANUFACTURING SYSTEM USING HYBRID PETRI NETS
Authors: ALLAM M ALLA H
Citation: M. Allam et H. Alla, MODELING AND SIMULATION OF AN ELECTRONIC-COMPONENT MANUFACTURING SYSTEM USING HYBRID PETRI NETS, IEEE transactions on semiconductor manufacturing, 11(3), 1998, pp. 374-383
SCHEDULING OF SEMICONDUCTOR TEST FACILITY VIA PETRI NETS AND HYBRID HEURISTIC-SEARCH
Authors: XIONG HH ZHOU MC
Citation: Hh. Xiong et Mc. Zhou, SCHEDULING OF SEMICONDUCTOR TEST FACILITY VIA PETRI NETS AND HYBRID HEURISTIC-SEARCH, IEEE transactions on semiconductor manufacturing, 11(3), 1998, pp. 384-393
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