MEASUREMENT AND CHARACTERIZATION OF MULTILAYERED INTERCONNECT CAPACITANCE FOR DEEP-SUBMICRON VLSI TECHNOLOGY

This paper presents the measurement and characterization of multilayer ed interconnect capacitances for a 0.35-mu m CMOS logic technology, wh ich become a critical circuit limitation to high performance VLSI desi gn. To measure multilayered capacitances of nonstacked, stacked, and o rthogonally crossing interconnect lines, new test structures and measu rement method are presented. The measured interconnect capacitances we re employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies. This study shows that the calib ration method considerably improves the accuracy of simulation results compared with measured results.