PLANNING WAFER ALLOCATION FOR CMOS PROCESS-DEVELOPMENT - A NONPARAMETRIC APPROACH

Citation
S. Rao et al., PLANNING WAFER ALLOCATION FOR CMOS PROCESS-DEVELOPMENT - A NONPARAMETRIC APPROACH, IEEE transactions on semiconductor manufacturing, 11(4), 1998, pp. 583-590
Citations number
7
Categorie Soggetti
Engineering, Eletrical & Electronic","Engineering, Manufacturing","Physics, Applied
ISSN journal
08946507
Volume
11
Issue
4
Year of publication
1998
Pages
583 - 590
Database
ISI
SICI code
0894-6507(1998)11:4<583:PWAFCP>2.0.ZU;2-X
Abstract
In this paper, we present techniques that can be used to answer the fo llowing two questions: 1) how many wafers need to be allocated per tre atment to detect a given difference in a device performance metric and 2) how can one determine if a given treatment significantly improved a performance metric? The approach presented here does not make any as sumptions regarding the shape of the distribution or the spatial depen dency structure for the within-wafer performance measurements and rema ins applicable for a variety of performance metrics, such as mean, var iance, and median. The analysis method can be used in decisions regard ing the appropriateness of allocating half or quarter wafer splits to a treatment. Furthermore, the approach allows us to evaluate and compa re within-wafer sampling strategies for comparing performance metrics from competing flows.