AN EXTRACTION METHOD TO DETERMINE INTERCONNECT PARASITIC PARAMETERS

Interconnect parasitic parameters in integrated circuits have signific ant impact on circuit speed. An accurate monitoring of these parameter s can help to improve interconnect performance during process developm ent, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are d estructive (such as SEM measurement) or can determine only partial par asitic parameters (such as large capacitor measurement), In this paper , we present a new method for extracting interconnect parasitic parame ters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method i s based on two test patterns of a same structure with different dimens ions. The structure consumes less wafer area than existing methods. Th e method shows good agreement with SEM measurement of dielectric thick ness in both nonglobal planarized and chemical-mechanical polished pro cesses, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer.