MODELING, QUALITATIVE-ANALYSIS, AND PERFORMANCE EVALUATION OF THE ETCHING AREA IN AN IC WAFER FABRICATION SYSTEM USING PETRI NETS

Integrated circuit (IC) wafer fabrication systems can be characterized as discrete event systems, Petri nets are tools that have been succes sfully used to model and analyze such systems. This paper reports a pr oject of applying Petri net methodologies to detailed modeling, qualit ative analysis, and performance evaluation of the etching area in a re al-world IC wafer fabrication system located in Taiwan's Hsinchu Scien ce-Based Industrial Park. To tackle the problem of building a large an d complex system model, a synthesis technique is used. The resultant e xtended net model is checked for important qualitative properties in m anufacturing, A simple control policy for deadlock prevention is propo sed, To obtain performance measures, simulation is used. The simulatio n result shows that except a small number of machines, the errors betw een the simulated and actual utilizations are less than 5%, The valida ted model can be used to answer many ''what-if'' questions, such as pr edicting the maximal throughput and bottleneck machines.