Authors: HORIUCHI T BURNETT JD HU CM

Citation: T. Horiuchi et al., BIPOLAR-TRANSISTOR DEGRADATION UNDER DYNAMIC HOT-CARRIER STRESS, Solid-state electronics, 38(4), 1995, pp. 787-789

Authors: HAYDEN JD BURNETT JD PFIESTER JR WOO MP

Citation: Jd. Hayden et al., A NEW TECHNIQUE FOR FORMING A SHALLOW LINK BASE IN A DOUBLE POLYSILICON BIPOLAR-TRANSISTOR, I.E.E.E. transactions on electron devices, 41(1), 1994, pp. 63-68

Authors: HAYDEN JD BURNETT JD PERERA AH MELE TC WALCZYK FW KAUSHIK V LAGE CS SEE YC

Citation: Jd. Hayden et al., INTEGRATION OF A DOUBLE-POLYSILICON EMITTER BASE SELF-ALIGNED BIPOLAR-TRANSISTOR INTO A 0.5-MU-M BICMOS TECHNOLOGY FOR FAST 4-MB SRAMS, I.E.E.E. transactions on electron devices, 40(6), 1993, pp. 1121-1128