Authors:
Namekawa, T
Miyano, S
Fukuda, R
Haga, R
Wada, O
Banba, H
Takeda, S
Suda, K
Mimoto, K
Yamaguchi, S
Ohkubo, T
Takato, H
Numata, K
Citation: T. Namekawa et al., Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus, IEEE J SOLI, 35(5), 2000, pp. 705-712