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Results:
1-2
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Results: 2
Switching activity evaluation of CMOS digital circuits using logic timing simulation
Authors:
Juan-Chico, J Bellido, MJ Ruiz-de-Clavijo, P Baena, C Jimenez, CJ Valencia, M
Citation:
J. Juan-chico et al., Switching activity evaluation of CMOS digital circuits using logic timing simulation, ELECTR LETT, 37(9), 2001, pp. 555-557
Inertial effect handling method for CMOS digital IC simulation
Authors:
Juan-Chico, J Bellido, MJ Acosta, AJ Valencia, M
Citation:
J. Juan-chico et al., Inertial effect handling method for CMOS digital IC simulation, ELECTR LETT, 35(23), 1999, pp. 2028-2030
Risultati:
1-2
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