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Threshold logic circuit design of parallel adders using resonant tunnelingdevices
Authors: Pacha, C Auer, U Burwick, C Glosekotter, P Brennemann, A Prost, W Tegude, FJ Goser, KF
Citation: C. Pacha et al., Threshold logic circuit design of parallel adders using resonant tunnelingdevices, IEEE VLSI, 8(5), 2000, pp. 558-572
Parallel adder design with reduced circuit complexity using resonant tunneling transistors and threshold logic
Authors: Pacha, C Kessler, O Glosekotter, P Goser, KF Prost, W Brennemann, A Auer, U Tegude, FJ
Citation: C. Pacha et al., Parallel adder design with reduced circuit complexity using resonant tunneling transistors and threshold logic, ANALOG IN C, 24(1), 2000, pp. 7-25
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