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Results: 1-5 |
Results: 5

Authors: Chakraborty, TJ Agrawal, VD Bushnell, ML
Citation: Tj. Chakraborty et al., Improving path delay testability of sequential circuits, IEEE VLSI, 8(6), 2000, pp. 736-741

Authors: Chakraborty, TJ Agrawal, VD Bushnell, ML
Citation: Tj. Chakraborty et al., Path delay fault simulation of sequential circuits, IEEE VLSI, 8(2), 2000, pp. 223-228

Authors: Gharaybeh, MA Agrawal, VD Bushnell, ML Parodi, CG
Citation: Ma. Gharaybeh et al., False-path removal using delay fault simulation, J ELEC TEST, 16(5), 2000, pp. 463-476

Authors: Iyer, MK Bushnell, ML
Citation: Mk. Iyer et Ml. Bushnell, Effect of noise on analog circuit testing, J ELEC TEST, 15(1-2), 1999, pp. 11-22

Authors: Ramadoss, R Bushnell, ML
Citation: R. Ramadoss et Ml. Bushnell, Test generation for mixed-signal devices using signal flow graphs, J ELEC TEST, 14(3), 1999, pp. 189-205
Risultati: 1-5 |