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Citation: Tj. Chakraborty et al., Improving path delay testability of sequential circuits, IEEE VLSI, 8(6), 2000, pp. 736-741

Authors: Chakraborty, TJ Agrawal, VD Bushnell, ML

Citation: Tj. Chakraborty et al., Path delay fault simulation of sequential circuits, IEEE VLSI, 8(2), 2000, pp. 223-228

Authors: Mukherjee, N Chakraborty, TJ

Citation: N. Mukherjee et Tj. Chakraborty, Built-in self-test: A complete test solution for telecommunication systems, IEEE COMM M, 37(6), 1999, pp. 72-78