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Results:
1-7
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Results: 7
Authors:
WUYTACK S
DIGUET JP
CATTHOOR FVM
DEMAN HJ
Citation: S. Wuytack et al., FORMALIZED METHODOLOGY FOR DATA REUSE EXPLORATION FOR LOW-POWER HIERARCHICAL MEMORY MAPPINGS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 529-537
Authors:
MIRANDA MA
CATTHOOR FVM
JANSSEN M
DEMAN HJ
Citation: Ma. Miranda et al., HIGH-LEVEL ADDRESS OPTIMIZATION AND SYNTHESIS TECHNIQUES FOR DATA-TRANSFER-INTENSIVE APPLICATIONS, IEEE transactions on very large scale integration (VLSI) systems, 6(4), 1998, pp. 677-686
Authors:
SCHAUMONT P
VANTHOURNOUT B
BOLSENS I
DEMAN HJ
Citation: P. Schaumont et al., SYNTHESIS OF PIPELINED DSP ACCELERATORS WITH DYNAMIC SCHEDULING, IEEE transactions on very large scale integration (VLSI) systems, 5(1), 1997, pp. 59-68
Authors:
BALASA F
CATTHOOR F
DEMAN HJ
Citation: F. Balasa et al., PRACTICAL SOLUTIONS FOR COUNTING SCALARS AND DEPENDENCES IN ATOMIUM -A MEMORY MANAGEMENT-SYSTEM FOR MULTIDIMENSIONAL SIGNAL-PROCESSING, IEEE transactions on computer-aided design of integrated circuits and systems, 16(2), 1997, pp. 133-145
Authors:
BOLSENS I
DEMAN HJ
LIN B
VANROMPAEY K
VERCAUTEREN S
VERKEST D
Citation: I. Bolsens et al., HARDWARE SOFTWARE CO-DESIGN OF DIGITAL TELECOMMUNICATION SYSTEMS/, Proceedings of the IEEE, 85(3), 1997, pp. 391-418
Authors:
WUYTACK S
CATTHOOR FVM
DEMAN HJ
Citation: S. Wuytack et al., TRANSFORMING SET DATA-TYPES TO POWER OPTIMAL DATA-STRUCTURES, IEEE transactions on computer-aided design of integrated circuits and systems, 15(6), 1996, pp. 619-629
Authors:
VANSAS J
CATTHOOR F
DEMAN HJ
Citation: J. Vansas et al., TEST ALGORITHMS FOR DOUBLE-BUFFERED RANDOM-ACCESS AND POINTER-ADDRESSED MEMORIES, IEEE design & test of computers, 10(2), 1993, pp. 34-44
Risultati:
1-7
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