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Results: 1-12 |
Results: 12
A CURRENT-MODE BASED FIELD-PROGRAMMABLE ANALOG ARRAY FOR SIGNAL-PROCESSING APPLICATIONS
Authors: EMBABI SHK QUAN X OKI N MANJREKAR A SANCHEZSINENCIO E
Citation: Shk. Embabi et al., A CURRENT-MODE BASED FIELD-PROGRAMMABLE ANALOG ARRAY FOR SIGNAL-PROCESSING APPLICATIONS, Analog integrated circuits and signal processing, 17(1-2), 1998, pp. 125-142
LOW-VOLTAGE CLASS AB BUFFERS WITH QUIESCENT CURRENT CONTROL
Authors: YOU F EMBABI SHK SANCHEZSINENCIO E
Citation: F. You et al., LOW-VOLTAGE CLASS AB BUFFERS WITH QUIESCENT CURRENT CONTROL, IEEE journal of solid-state circuits, 33(6), 1998, pp. 915-920
IMPROVED FULLY-BALANCED CURRENT-MODE INTEGRATOR
Authors: QUAN XH EMBABI SHK SANCHEZSINENCIO E
Citation: Xh. Quan et al., IMPROVED FULLY-BALANCED CURRENT-MODE INTEGRATOR, Electronics Letters, 34(1), 1998, pp. 1-3
ON THE COMMON-MODE REJECTION RATIO IN LOW-VOLTAGE OPERATIONAL-AMPLIFIERS WITH COMPLEMENTARY N-P INPUT PAIRS
Authors: YOU F EMBABI SHK SANCHEZSINENCIO E
Citation: F. You et al., ON THE COMMON-MODE REJECTION RATIO IN LOW-VOLTAGE OPERATIONAL-AMPLIFIERS WITH COMPLEMENTARY N-P INPUT PAIRS, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 44(8), 1997, pp. 678-683
AN IMPROVED TAIL CURRENT SOURCE FOR LOW-VOLTAGE APPLICATIONS
Authors: YOU F EMBABI SHK DUQUECARRILLO JF SANCHEZSINENCIO E
Citation: F. You et al., AN IMPROVED TAIL CURRENT SOURCE FOR LOW-VOLTAGE APPLICATIONS, IEEE journal of solid-state circuits, 32(8), 1997, pp. 1173-1180
MULTISTAGE AMPLIFIER TOPOLOGIES WITH NESTED G(M)-C COMPENSATION
Authors: YOU F EMBABI SHK SANCHEZSINENCIO E
Citation: F. You et al., MULTISTAGE AMPLIFIER TOPOLOGIES WITH NESTED G(M)-C COMPENSATION, IEEE journal of solid-state circuits, 32(12), 1997, pp. 2000-2011
BOOTSTRAPPED FULL-SWING BICMOS BINMOS LOGIC-CIRCUITS FOR 1.2-3.3 V SUPPLY VOLTAGE REGIME/
Authors: BELLAOUAR A ELMASRY MI EMBABI SHK
Citation: A. Bellaouar et al., BOOTSTRAPPED FULL-SWING BICMOS BINMOS LOGIC-CIRCUITS FOR 1.2-3.3 V SUPPLY VOLTAGE REGIME/, IEEE journal of solid-state circuits, 30(6), 1995, pp. 629-636
A BOOTSTRAPPED BIPOLAR CMOS (B(2)CMOS) GATE FOR LOW-VOLTAGE APPLICATIONS
Authors: EMBABI SHK BELLAOUAR A ISLAM K
Citation: Shk. Embabi et al., A BOOTSTRAPPED BIPOLAR CMOS (B(2)CMOS) GATE FOR LOW-VOLTAGE APPLICATIONS, IEEE journal of solid-state circuits, 30(1), 1995, pp. 47-53
A DYNAMIC CLOCK SYNCHRONIZATION TECHNIQUE FOR LARGE SYSTEMS
Authors: BRUESKE DE EMBABI SHK
Citation: De. Brueske et Shk. Embabi, A DYNAMIC CLOCK SYNCHRONIZATION TECHNIQUE FOR LARGE SYSTEMS, IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 17(3), 1994, pp. 350-361
DELAY MODELS FOR CMOS, BICMOS AND BINMOS CIRCUITS AND THEIR APPLICATIONS FOR TIMING SIMULATIONS
Authors: EMBABI SHK DAMODARAN R
Citation: Shk. Embabi et R. Damodaran, DELAY MODELS FOR CMOS, BICMOS AND BINMOS CIRCUITS AND THEIR APPLICATIONS FOR TIMING SIMULATIONS, IEEE transactions on computer-aided design of integrated circuits and systems, 13(9), 1994, pp. 1132-1142
A BICMOS LOW-POWER CURRENT-MODE GATE
Authors: EMBABI SHK BRUESKE DE RACHAMREDDY K
Citation: Shk. Embabi et al., A BICMOS LOW-POWER CURRENT-MODE GATE, IEEE journal of solid-state circuits, 29(6), 1994, pp. 741-745
NOVEL PLL-BASED CLOCK DISTRIBUTION SCHEME
Authors: EMBABI SHK ISLAM KI
Citation: Shk. Embabi et Ki. Islam, NOVEL PLL-BASED CLOCK DISTRIBUTION SCHEME, Electronics Letters, 29(21), 1993, pp. 1813-1814
Risultati: 1-12 |