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Results: 1-25 | 26-30 |
Results: 26-30/30
MODELING OF ULTRATHIN DOUBLE-GATE NMOS SOI TRANSISTORS/
Authors: FRANCIS P TERAO A FLANDRE D VANDEWIELE F
Citation: P. Francis et al., MODELING OF ULTRATHIN DOUBLE-GATE NMOS SOI TRANSISTORS/, I.E.E.E. transactions on electron devices, 41(5), 1994, pp. 715-720
COMPARISON OF SOI VERSUS BULK PERFORMANCE OF CMOS MICROPOWER SINGLE-STAGE OTAS
Authors: FLANDRE D EGGERMONT JP DECEUSTER D JESPERS P
Citation: D. Flandre et al., COMPARISON OF SOI VERSUS BULK PERFORMANCE OF CMOS MICROPOWER SINGLE-STAGE OTAS, Electronics Letters, 30(23), 1994, pp. 1933-1934
P+-P-P+ PSEUDO-BIPOLAR LATERAL SOI TRANSISTOR
Authors: COLINGE JP FLANDRE D DECEUSTER D
Citation: Jp. Colinge et al., P+-P-P+ PSEUDO-BIPOLAR LATERAL SOI TRANSISTOR, Electronics Letters, 30(18), 1994, pp. 1543-1545
KINK-LIKE EFFECT IN LONG N-CHANNEL TWIN-GATE FULLY-DEPLETED SOI MOSFETS
Authors: DECEUSTER D FLANDRE D
Citation: D. Deceuster et D. Flandre, KINK-LIKE EFFECT IN LONG N-CHANNEL TWIN-GATE FULLY-DEPLETED SOI MOSFETS, Electronics Letters, 30(17), 1994, pp. 1456-1458
ANALYSIS OF FLOATING SUBSTRATE EFFECTS ON THE INTRINSIC GATE CAPACITANCE OF SOI MOSFETS USING 2-DIMENSIONAL DEVICE SIMULATION
Authors: FLANDRE D
Citation: D. Flandre, ANALYSIS OF FLOATING SUBSTRATE EFFECTS ON THE INTRINSIC GATE CAPACITANCE OF SOI MOSFETS USING 2-DIMENSIONAL DEVICE SIMULATION, I.E.E.E. transactions on electron devices, 40(10), 1993, pp. 1789-1796
Risultati: 1-25 | 26-30 |