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Results: 1-10 |
Results: 10
MORPHOLOGY AND CRYSTALLOGRAPHY OF ALPHA-PRECIPITATE IN BETA-TI-MO BINARY-ALLOYS
Authors: FURUHARA T MAKINO T IDEI Y ISHIGAKI H TAKADA A MAKI T
Citation: T. Furuhara et al., MORPHOLOGY AND CRYSTALLOGRAPHY OF ALPHA-PRECIPITATE IN BETA-TI-MO BINARY-ALLOYS, Materials transactions, JIM, 39(1), 1998, pp. 31-39
DUAL-PERIOD SELF-REFRESH SCHEME FOR LOW-POWER DRAMS WITH ON-CHIP PROMMODE REGISTER
Authors: IDEI Y SHIMOHIGASHI K AOKI M NODA H IWAI H SATO K TACHIBANA T
Citation: Y. Idei et al., DUAL-PERIOD SELF-REFRESH SCHEME FOR LOW-POWER DRAMS WITH ON-CHIP PROMMODE REGISTER, IEEE journal of solid-state circuits, 33(2), 1998, pp. 253-259
REDUNDANCY CIRCUIT FOR A SUBNANOSECOND, MEGABIT ECL-CMOS SRAM
Authors: OHHATA K KUSUNOKI T NAMBU H KANETANI K MASUDA T OHAYASHI M HAMAMOTO S YAMAGUCHI K IDEI Y HOMMA N
Citation: K. Ohhata et al., REDUNDANCY CIRCUIT FOR A SUBNANOSECOND, MEGABIT ECL-CMOS SRAM, IEICE transactions on electronics, E79C(3), 1996, pp. 415-423
OVARIAN SMALL-CELL CARCINOMA WITH K-RAS MUTATION - A CASE-REPORT WITHGENETIC-ANALYSIS
Authors: IDEI Y KITAZAWA S FUJIMORI T AJIKI T ASAKA K TAKEUCHI S MOCHIZUKI M CHIBA T MAEDA S
Citation: Y. Idei et al., OVARIAN SMALL-CELL CARCINOMA WITH K-RAS MUTATION - A CASE-REPORT WITHGENETIC-ANALYSIS, Human pathology, 27(1), 1996, pp. 77-79
A SOFT-ERROR-IMMUNE 0.9-NS 1.15-MB ECL-CMOS SRAM WITH 30-PS 120 K LOGIC GATES AND ON-CHIP TEST CIRCUITRY
Authors: HIGETA K USAMI M OHAYASHI M FUJIMURA Y NISHIYAMA M ISOMURA S YAMAGUCHI K IDEI Y NAMBU H OHHATA K HANTA N
Citation: K. Higeta et al., A SOFT-ERROR-IMMUNE 0.9-NS 1.15-MB ECL-CMOS SRAM WITH 30-PS 120 K LOGIC GATES AND ON-CHIP TEST CIRCUITRY, IEEE journal of solid-state circuits, 31(10), 1996, pp. 1443-1450
A 0.65-NS, 72-KB ECL-CMOS RAM MACRO FOR A 1-MB SRAM
Authors: NAMBU H KANETANI K IDEI Y MASUDA T HIGETA K OHAYASHI M USAMI M YAMAGUCHI K KIKUCHI T IKEDA T OHHATA K KUSUNOKI T HOMMA N
Citation: H. Nambu et al., A 0.65-NS, 72-KB ECL-CMOS RAM MACRO FOR A 1-MB SRAM, IEICE transactions on electronics, E78C(6), 1995, pp. 739-747
SELF-ALIGNED COMPLEMENTARY BIPOLAR TECHNOLOGY FOR LOW-POWER DISSIPATION AND ULTRA-HIGH-SPEED LSIS
Authors: ONAI T OHUE E IDEI Y TANABE M SHIMAMOTO H WASHIO K NAKAMURA T
Citation: T. Onai et al., SELF-ALIGNED COMPLEMENTARY BIPOLAR TECHNOLOGY FOR LOW-POWER DISSIPATION AND ULTRA-HIGH-SPEED LSIS, I.E.E.E. transactions on electron devices, 42(3), 1995, pp. 413-418
A 0.65-NS, 72-KB ECL-CMOS RAM MACRO FOR A 1-MB SRAM
Authors: NAMBU H KANETANI K IDEI Y MASUDA T HIGETA K OHAYASHI M USAMI M YAMAGUCHI K KIKUCHI T IKEDA T OHHATA K KUSUNOKI T HOMMA N
Citation: H. Nambu et al., A 0.65-NS, 72-KB ECL-CMOS RAM MACRO FOR A 1-MB SRAM, IEEE journal of solid-state circuits, 30(4), 1995, pp. 491-499
REDUNDANCY TECHNIQUE FOR ULTRA-HIGH-SPEED STATIC RAMS
Authors: NAMBU H KANETANI K IDEI Y YAMAGUCHI K HIRAMOTO T TAMBA N WATANABE K ODAKA M IKEDA T OHHATA K SAKURAI Y HOMMA N
Citation: H. Nambu et al., REDUNDANCY TECHNIQUE FOR ULTRA-HIGH-SPEED STATIC RAMS, IEICE transactions on electronics, E76C(4), 1993, pp. 641-648
NOISE-REDUCTION TECHNIQUES FOR A 64-KB ECL-CMOS SRAM WITH A 2-NS CYCLE TIME
Authors: OHHATA K SAKURAI Y NAMBU H KANETANI K IDEI Y HIRAMOTO T TAMBA N YAMAGUCHI K ODAKA M WATANABE K IKEDA T HOMMA N
Citation: K. Ohhata et al., NOISE-REDUCTION TECHNIQUES FOR A 64-KB ECL-CMOS SRAM WITH A 2-NS CYCLE TIME, IEICE transactions on electronics, E76C(11), 1993, pp. 1611-1619
Risultati: 1-10 |