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Authors: NAKAMURA H MIYAMOTO J IMAMIYA K IWATA Y SUGIURA Y OODAIRA H
Citation: H. Nakamura et al., A NOVEL SENSING SCHEME WITH ON-CHIP PAGE COPY FOR FLEXIBLE VOLTAGE NAND FLASH MEMORIES, IEICE transactions on electronics, E79C(6), 1996, pp. 836-844

Authors: IWATA Y IMAMIYA K SUGIURA Y NAKAMURA H OODAIRA H MOMODOMI M ITOH Y WATANABE T ARAKI H NARITA K MASUDA K MIYAMOTO J
Citation: Y. Iwata et al., A 35 NS CYCLE TIME 3.3 V ONLY 32 MB NAND FLASH EEPROM, IEEE journal of solid-state circuits, 30(11), 1995, pp. 1157-1164

Authors: IMAMIYA K MIYAMOTO J OHTSUKA N TOMITA N IYAMA Y
Citation: K. Imamiya et al., STATISTICAL MEMORY YIELD ANALYSIS AND REDUNDANCY DESIGN CONSIDERING FABRICATION LINE IMPROVEMENT, IEICE transactions on electronics, E76C(11), 1993, pp. 1626-1631
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