Authors:
Maeda, S
Wada, Y
Yamamoto, K
Komurasaki, H
Matsumoto, T
Hirano, Y
Iwamatsu, T
Yamaguchi, Y
Ipposhi, T
Ueda, K
Mashiko, K
Maegawa, S
Inuishi, M
Citation: S. Maeda et al., Feasibility of 0.18 mu m SOI CMOS technology using hybrid trench isolationwith high resistivity substrate for embedded RF/analog applications, IEEE DEVICE, 48(9), 2001, pp. 2065-2073
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Authors:
Iwamatsu, T
Nakayama, K
Takaoka, H
Takai, M
Yamaguchi, Y
Maegawa, S
Inuishi, M
Kinomura, A
Horino, Y
Nishimura, T
Citation: T. Iwamatsu et al., Direct measurement of transient drain cuff rents in partially-depleted SOIN-channel MOSFETs using a nuclear microprobe for highly reliable device designs, JPN J A P 1, 39(4B), 2000, pp. 2236-2240
Authors:
Shimizu, M
Mitsui, K
Inuishi, M
Arima, H
Hamaguchi, C
Citation: M. Shimizu et al., Scalability of gate/N- overlapped lightly doped drain in deep-submicrometer regime, JPN J A P 1, 37(12A), 1998, pp. 6340-6347
Authors:
Shimizu, M
Kuroi, T
Inuishi, M
Arima, H
Abe, K
Hamaguchi, C
Citation: M. Shimizu et al., Subquarter-micrometer dual gate complementary metal oxide semiconductor field effect transistor with ultrathin gate oxide of 2 nm, JPN J A P 1, 37(11), 1998, pp. 5926-5931