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Results: 1-5 |
Results: 5

Authors: JHANG KS HA S JHON CS
Citation: Ks. Jhang et al., SIMULATED ANNEALING APPROACH TO CROSSTALK MINIMIZATION IN GRIDDED CHANNEL ROUTING, VLSI design, 7(1), 1998, pp. 85-95

Authors: KIM JS HA S JHON CS
Citation: Js. Kim et al., RELAXED BARRIER SYNCHRONIZATION FOR THE BSP MODEL OF COMPUTATION ON MESSAGE-PASSING ARCHITECTURES, Information processing letters, 66(5), 1998, pp. 247-253

Authors: YI K OHM SY JHON CS
Citation: K. Yi et al., AN EFFICIENT FPGA TECHNOLOGY MAPPING TIGHTLY COUPLED WITH LOGIC MINIMIZATION, IEICE transactions on fundamentals of electronics, communications and computer science, E80A(10), 1997, pp. 1807-1812

Authors: JHANG KS HA S JHON CS
Citation: Ks. Jhang et al., COP - A CROSSTALK OPTIMIZER FOR GRIDDED CHANNEL ROUTING, IEEE transactions on computer-aided design of integrated circuits and systems, 15(4), 1996, pp. 424-429

Authors: OHM SY KURDAHI FJ JHON CS
Citation: Sy. Ohm et al., AN OPTIMAL SCHEDULING APPROACH USING LOWER-BOUND IN HIGH-LEVEL SYNTHESIS, IEICE transactions on information and systems, E78D(3), 1995, pp. 231-236
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