Authors: Krstic, A Jiang, YM Cheng, KT

Citation: A. Krstic et al., Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects, IEEE COMP A, 20(3), 2001, pp. 416-425

Authors: Jiang, YM Krstic, A Cheng, KT

Citation: Ym. Jiang et al., Estimation for maximum instantaneous current through supply lines for CMOScircuits, IEEE VLSI, 8(1), 2000, pp. 61-73

Authors: Lai, WC Krstic, A Cheng, KT

Citation: Wc. Lai et al., Functionally testable path delay faults on a microprocessor, IEEE DES T, 17(4), 2000, pp. 6-14

Authors: Krstic, A Cheng, KT Chakradhar, ST

Citation: A. Krstic et al., Primitive delay faults: Identification, testing, and design for testability, IEEE COMP A, 18(6), 1999, pp. 669-684

Authors: Cheng, KT Krstic, A

Citation: Kt. Cheng et A. Krstic, Current directions in automatic test-pattern generation, COMPUTER, 32(11), 1999, pp. 58