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Results: 3
A JOINT GATE SIZING AND BUFFER INSERTION METHOD FOR OPTIMIZING DELAY AND POWER IN CMOS AND BICMOS COMBINATIONAL LOGIC
Authors: LOWE KS GULAK PG
Citation: Ks. Lowe et Pg. Gulak, A JOINT GATE SIZING AND BUFFER INSERTION METHOD FOR OPTIMIZING DELAY AND POWER IN CMOS AND BICMOS COMBINATIONAL LOGIC, IEEE transactions on computer-aided design of integrated circuits and systems, 17(5), 1998, pp. 419-434
A GAAS HBT 16X16 10-GB S/CHANNEL CROSSPOINT SWITCH/
Authors: LOWE KS
Citation: Ks. Lowe, A GAAS HBT 16X16 10-GB S/CHANNEL CROSSPOINT SWITCH/, IEEE journal of solid-state circuits, 32(8), 1997, pp. 1263-1268
BUFFERLESS BROADCASTING - A LOW-POWER DISTRIBUTED CIRCUIT TECHNIQUE FOR BROADCASTING 10-GB S CHIP INPUT SIGNALS/
Authors: LOWE KS
Citation: Ks. Lowe, BUFFERLESS BROADCASTING - A LOW-POWER DISTRIBUTED CIRCUIT TECHNIQUE FOR BROADCASTING 10-GB S CHIP INPUT SIGNALS/, IEEE journal of solid-state circuits, 32(10), 1997, pp. 1551-1555
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