Citation: G. Notermans et al., USING AN SCR AS ESD PROTECTION WITHOUT LATCH-UP DANGER, Microelectronics and reliability, 37(10-11), 1997, pp. 1457-1460
Authors:
VERHAEGE K
RUSS C
LUCHIES JM
GROESENEKEN G
KUPER FG
Citation: K. Verhaege et al., GROUNDED-GATE NMOS TRANSISTOR BEHAVIOR UNDER CDM ESD STRESS CONDITIONS, I.E.E.E. transactions on electron devices, 44(11), 1997, pp. 1972-1980
Citation: F. Kuper et al., SUPPRESSION AND ORIGIN OF SOFT ESD FAILURES IN A SUBMICRON CMOS PROCESS, Journal of electrostatics, 33(3), 1994, pp. 313-325