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Results:
1-10
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Results: 10
Authors:
Larus, JR
Parkes, M
Citation: Jr. Larus et M. Parkes, Using cohort scheduling to enhance server performance, ACM SIGPL N, 36(8), 2001, pp. 182-187
Authors:
Schnarr, EC
Hill, MD
Larus, JR
Citation: Ec. Schnarr et al., Facile: A language and compiler for high-performance processor simulators, ACM SIGPL N, 36(5), 2001, pp. 321-331
Authors:
Mukherjee, SS
Reinhardt, SK
Falsafi, B
Litzkow, M
Hill, MD
Wood, DA
Huss-Lederman, S
Larus, JR
Citation: Ss. Mukherjee et al., Wisconsin Wind Tunnel II: A fast, portable parallel architecture simulator, IEEE CONCUR, 8(4), 2000, pp. 12-20
Authors:
Ball, T
Larus, JR
Citation: T. Ball et Jr. Larus, Using paths to measure, explain, and enhance program behavior, COMPUTER, 33(7), 2000, pp. 57
Authors:
Chilimbi, TM
Hill, MD
Larus, JR
Citation: Tm. Chilimbi et al., Making pointer-based data structures cache conscious, COMPUTER, 33(12), 2000, pp. 67
Authors:
Chilimbi, TM
Hill, MD
Larus, JR
Citation: Tm. Chilimbi et al., Cache-conscious structure layout, ACM SIGPL N, 34(5), 1999, pp. 1-12
Authors:
Chilimbi, TM
Davidson, B
Larus, JR
Citation: Tm. Chilimbi et al., Cache-conscious structure definition, ACM SIGPL N, 34(5), 1999, pp. 13-24
Authors:
Larus, JR
Citation: Jr. Larus, Whole program paths, ACM SIGPL N, 34(5), 1999, pp. 259-269
Authors:
Chilimbi, TM
Larus, JR
Citation: Tm. Chilimbi et Jr. Larus, Using generational garbage collection to implement cache-conscious data placement, ACM SIGPL N, 34(3), 1999, pp. 37-48
Authors:
Chandra, S
Richards, B
Larus, JR
Citation: S. Chandra et al., Teapot: A domain-specific language for writing cache coherence protocols, IEEE SOFT E, 25(3), 1999, pp. 317-333
Risultati:
1-10
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