AAAAAA

   
Results: 1-5 |
Results: 5

Authors: LARSSONEDEFORS P MARNANE WP
Citation: P. Larssonedefors et Wp. Marnane, MOST-SIGNIFICANT-BIT-FIRST SERIAL PARALLEL MULTIPLIERS/, IEE proceedings. Circuits, devices and systems, 145(4), 1998, pp. 278-284

Authors: MARNANE WP
Citation: Wp. Marnane, OPTIMIZED BIT-SERIAL MODULAR MULTIPLIER FOR IMPLEMENTATION ON FIELD-PROGRAMMABLE GATE ARRAYS, Electronics Letters, 34(8), 1998, pp. 738-739

Authors: BELLIS SJ MARNANE WP FISH PJ
Citation: Sj. Bellis et al., ALTERNATIVE SYSTOLIC ARRAY FOR NON-SQUARE-ROOT CHOLESKY DECOMPOSITION, IEE proceedings. Computers and digital techniques, 144(2), 1997, pp. 57-64

Authors: MARNANE WP BELLIS SJ LARSSONEDEFORS P
Citation: Wp. Marnane et al., BIT-SERIAL INTERLEAVED HIGH-SPEED DIVISION, Electronics Letters, 33(13), 1997, pp. 1124-1125

Authors: MARNANE WP MOORE WR
Citation: Wp. Marnane et Wr. Moore, TESTING VLSI REGULAR ARRAYS, JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 6(2), 1995, pp. 153-177
Risultati: 1-5 |