Authors: MAHARANA GS MEHER PK

Citation: Gs. Maharana et Pk. Meher, ALGORITHM FOR EFFICIENT INTERPOLATION OF REAL-VALUED SIGNALS USING DISCRETE HARTLEY TRANSFORM, Computers & electrical engineering, 23(2), 1997, pp. 129-134

Authors: NAYAK SS MEHER PK

Citation: Ss. Nayak et Pk. Meher, 3-DIMENSIONAL SYSTOLIC ARCHITECTURE FOR PARALLEL VLSI IMPLEMENTATION OF THE DISCRETE COSINE TRANSFORM, IEE proceedings. Circuits, devices and systems, 143(5), 1996, pp. 255-258

Authors: MOHANTY BK MEHER PK

Citation: Bk. Mohanty et Pk. Meher, COST-EFFECTIVE NOVEL FLEXIBLE CELL-LEVEL SYSTOLIC ARCHITECTURE FOR HIGH-THROUGHPUT IMPLEMENTATION OF 2-D FIR FILTERS, IEE proceedings. Computers and digital techniques, 143(6), 1996, pp. 436-439

Authors: MEHER PK PANDA G

Citation: Pk. Meher et G. Panda, UNCONSTRAINED HARTLEY DOMAIN LEAST MEAN-SQUARE ADAPTIVE FILTER, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 40(9), 1993, pp. 582-585

Authors: MEHER PK SATAPATHY JK PANDA G

Citation: Pk. Meher et al., EFFICIENT SYSTOLIC SOLUTION FOR A NEW PRIME FACTOR DISCRETE HARTLEY TRANSFORM ALGORITHM, IEE proceedings. Part G. Circuits, devices and systems, 140(2), 1993, pp. 135-139

Authors: MEHER PK PANDA G

Citation: Pk. Meher et G. Panda, NOVEL RECURSIVE ALGORITHM AND HIGHLY COMPACT SEMISYSTOLIC ARCHITECTURE FOR HIGH-THROUGHPUT COMPUTATION OF 2-D DHT, Electronics Letters, 29(10), 1993, pp. 883-885