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Results:
1-8
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Results: 8
Authors:
Benini, L
Castelli, G
Macii, A
Mach, E
Poncino, M
Scarsi, R
Citation: L. Benini et al., Discrete-time battery models for system-level low-power design, IEEE VLSI, 9(5), 2001, pp. 630-640
Authors:
Macii, A
Macii, E
Poncino, M
Scarsi, R
Citation: A. Macii et al., Stream synthesis for efficient power simulation based on spectral transforms, IEEE VLSI, 9(3), 2001, pp. 417-426
Authors:
Benini, L
Castelli, G
Macii, A
Scarsi, R
Citation: L. Benini et al., Battery-driven dynamic power management, IEEE DES T, 18(2), 2001, pp. 53-60
Authors:
Benini, L
De Micheli, D
Macii, A
Macii, E
Poncino, M
Scarsi, R
Citation: L. Benini et al., Glitch power minimization by selective gate freezing, IEEE VLSI, 8(3), 2000, pp. 287-298
Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation
Authors:
Benini, L
Macii, A
Macii, E
Poncino, M
Citation: L. Benini et al., Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation, IEEE DES T, 17(2), 2000, pp. 74-85
Authors:
Benini, L
Macii, A
Macii, E
Poncino, M
Scarsi, R
Citation: L. Benini et al., Architectures and synthesis algorithms for power-efficient bus interfaces, IEEE COMP A, 19(9), 2000, pp. 969-980
Authors:
Baldi, M
Macii, A
Macii, E
Poncino, R
Citation: M. Baldi et al., Application of symbolic FSM Markovian analysis to protocol verification, IEE P-COM D, 146(5), 1999, pp. 221-226
Authors:
Benini, L
De Micheli, G
Macii, A
Macii, E
Poncino, M
Citation: L. Benini et al., Automatic selection of instruction op-codes of low-power core processors, IEE P-COM D, 146(4), 1999, pp. 173-178
Risultati:
1-8
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